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SWITCHING CHARACTERISTICS
Characteristic
Output Rise and Fall Time
t TLH , t THL = (1.5 ns/pF) C L + 25 ns
t TLH , t THL = (0.75 ns/pF) C L + 12.5 ns
t TLH , t THL = (0.55 ns/pF) C L + 9.5 ns
Propagation Delay Time (Figure 2)
Inhibit, Control, or Data to Z
Propagation Delay Time (Figure 2)
Inhibit, Control, or Data to Z
3–State Output Delay Times (Figure 3)
"1" or "0" to High Z, and
High Z to "1" or "0"
* The formulas given are for the typical characteristics only at 25 _ C.
#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
V in
V DD
DISABLE
INHIBIT
A
B
C
X0
PULSE
X1
GENERATOR
X2
X3
X4
X5
X6
X7
MC14512B
6–264
(C L = 50 pF, T A = 25 _ C, See Figure 1)
PULSE
50%
GENERATOR
50%
DUTY
CYCLE
Figure 1. Power Dissipation Test Circuit and Waveform
Z
C L
V SS
Parameter
Inhibit to Z
A, B, C = V SS , X O = V DD
A, B, C to Z
Inh = V SS , X O = V DD
Figure 2. AC Test Circuit and Waveforms
Symbol
V DD
t TLH ,
t THL
5.0
10
15
t PLH
5.0
10
15
t PHL
5.0
10
15
t PHZ , t PLZ ,
5.0
t PZH , t PZL
10
15
I D
DISABLE
INHIBIT
Z
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
V SS
20 ns
DATA
t PLH
Z
20 ns
INHIBIT,
A, B, OR C
t PHL
Test Conditions
Z
All Types
Typ #
Max
Unit
100
200
50
100
40
80
330
650
125
250
85
170
330
650
125
250
85
170
60
150
35
100
30
75
V DD
C L
20 ns
90%
50%
10%
t PHL
90%
50%
10%
t TLH
t THL
TEST CONDITIONS:
INHIBIT = V SS
A, B, C = V SS
20 ns
90%
50%
10%
t PLH
90%
50%
10%
t THL
t TLH
MOTOROLA CMOS LOGIC DATA
ns
ns
ns
ns
V DD
V SS
V OH
V OL
V DD
V SS
V OH
V OL
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