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These counters are fully programmable; that is the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after the
next clock pulse regardless of the levels of the enable inputs.
The clear function for the MC14160B, MC14161B is asynch–
ronous and a low level at the clear input sets all four of the
flip—flop outputs low regardless of the levels of the clock,
load or enable inputs. The clear function for the MC14162B
and MC14163B is synchronous and a low level at the clear
inputs sets all four of the flip—flop outputs low after the next
clock pulse, regardless of the levels of the enable inputs.
This synchronous clear allows the count length to be modi-
fied easily; decoding the maximum count desired can be ac-
MC14160B MC14161B MC14162B MC14163B
6–188
SWITCHING WAVEFORMS
FUNCTIONAL DESCRIPTION
complished with one external NAND gate. The gate output is
connected to the clear input to synchronously clear the
counter to 0000(LLLL).
The carry look—ahead circuitry provides for cascading
counters for n—bit synchronous applications without addi-
tional gating. Instrumental in accomplishing this function are
two count—enable inputs and a carry output. Both count—
enable inputs (PE, TE) must be high to count, and enable in-
put TE fed forward to enable the carry output. The carry
output thus enabled will produce a positive output pulse with
a duration approximately equal to the positive portion of the
Q1 output. This positive overflow carry pulse can be used to
enable successive cascaded stages.
MOTOROLA CMOS LOGIC DATA
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