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V DD
500 µF
I D
SET
RESET
OUT 1
8–BYPASS
PULSE
IN 1
GENERATOR
C INH
OUT
MONO IN
OSC INH
A
B
C
DECODE
OUT
D
V SS
20 ns
90%
50%
10%
50%
DUTY CYCLE
Figure 6. Power Dissipation Test
Circuit and Waveform
FUNCTIONAL TEST SEQUENCE
Test function (Figure 8) has been included for the reduc-
tion of test time required to exercise all 24 counter stages.
This test function divides the counter into three 8–stage
sections and 255 counts are loaded in each of the 8–stage
sections in parallel. All flip–flops are now at a "1". The count-
er is now returned to the normal 24–stages in series configu-
ration. One more pulse is entered into In 1 which will cause
the counter to ripple from an all "1" state to an all "0" state.
Inputs
In 1
Set
Reset
1
0
1
1
1
1
0
1
1
1
0
—
1
1
—
—
0
1
1
0
0
0
1
0
0
0
0
0
MOTOROLA CMOS LOGIC DATA
0.01 µF
CERAMIC
C L
2
C L
PULSE
GENERATOR
C L
20 ns
FUNCTIONAL TEST SEQUENCE
Outputs
Decade Out
Q1 thru Q24
8–Bypass
1
0
1
0
1
0
1
1
1
0
1
0
1
0
0
20 ns
V DD
IN 1
SET
OUT 1
RESET
OUT
8–BYPASS
IN 1
t PLH
C INH
OUT
MONO IN
2
OSC INH
A
B
C
DECODE
OUT
D
V SS
Figure 7. Switching Time Test Circuit and Waveforms
PULSE
GENERATOR
Figure 8. Functional Test Circuit
Comments
All 24 stages are in Reset mode.
g
Counter is in three 8 stage sections in parallel mode.
First "1" to "0" transition of clock.
255 "1" to "0" transitions are clocked in the counter.
The 255 "1" to "0" transition.
Counter converted back to 24 stages in series mode.
Set and Reset must be connected together and simultaneously
go from "1" to "0".
In 1 Switches to a "1".
Counter Ripples from an all "1" state to an all "0" state.
20 ns
50%
t WL
t WH
90%
10%
t TLH
t THL
C L
V DD
SET
RESET
OUT 1
8–BYPASS
IN 1
C INH
MONO IN
OUT
2
OSC INH
A
B
C
DECODE
OUT
D
V SS
MC14536B
6–361
50%
t PHL
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