Motorola CMOS Logic Manual page 293

CLOCK (f in )
RESET
+ V DD
OPEN = COUNT
Note: The programmable frequency divider can be set by applying the desired divide ratio, in BCD, to the preset inputs. For
example, the maximum divide ratio of 99 may be obtained by applying a 10011001 to the preset inputs P0 to P7. For this divide
operation, both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and
should be avoided.
MOTOROLA CMOS LOGIC DATA
Q0 Q1 Q2 Q3
Q1 Q2 Q3 Q4
PE
C in C out
L.S.D.
CLOCK
MC14510B
U/D
R
P1 P2 P3 P4
P0 P1 P2 P3
+ V DD
THUMBWHEEL SWITCHES
(OPEN FOR "0")
Figure 4. Programmable Cascaded Frequency Divider
Q4 Q5 Q6 Q7
Q1 Q2 Q3 Q4
PE
C in C out
M.S.D.
CLOCK
MC14510B
U/D
R
P1 P2 P3 P4
P4 P5 P6 P7
+ V DD
RESISTORS = 10 kΩ
f in
f out =
n
f out
BUFFER
MC14510B
6–255