Motorola CMOS Logic Manual page 127

CARRY IN OR
UP/DOWN
OR BINARY/DECADE
CLOCK
PRESET ENABLE
Q0 OR CARRY OUT
MOTOROLA CMOS LOGIC DATA
500 pF
PE
C in
B/D
U/D
PULSE
CLK
GENERATOR
P0
P1
P2
P3
20 ns
50%
CLK
VARIABLE
WIDTH
Figure 1. Power Dissipation Test Circuit and Waveform
PROGRAMMABLE
PULSE
GENERATOR
t W
t su
50%
50%
t W
C out ONLY
90%
10%
t THL t PHL
Figure 2. Switching Time Test Circuit and Waveforms
V DD
0.01 µF
I D
CERAMIC
Q0
Q1
Q2
C L
C L
Q3
C L
C out
C L
C L
20 ns
V DD
90%
10%
V SS
V DD
PE Q0
C in
B/D Q1
U/D
CLK Q2
P0
P1 Q3
P2
P3 C out C L
C L
V SS
t rem
1/f cl
20 ns
t TLH
90%
10%
t PLH
t PLH
C L
C L
C L
V DD
V SS
V DD
V SS
V DD
V SS
V OH
V OL
MC14029B
6–89