Motorola CMOS Logic Manual page 242

Parallel Load
3
4
5
6
11
PULSE
2
GENERATOR
7
9
10
1
20 ns
DPn
DSR
50%
DSL
10%
CLOCK
Q n
RESET
3
4
5
6
11
PULSE
2
GENERATOR
7
9
10
1
Figure 2. Dynamic Power Dissipation Test Circuit and Waveforms
MC14194B
6–204
V DD
16
15
D P0 Q0
C L
D P1
D P2
14
Q1
D P3
C L
CLOCK
13
DSR
Q2
DSL
C L
S0
12
S1 Q3
R
C L
8 V SS
20 ns
90%
t h
t su
t su
50%
t WH(cl)
t PLH
90%
50%
10%
t TLH
Figure 1. Switching Time Test Circuits and Waveforms
V DD
16
15
D P0 Q0
C L
D P1
D P2
14
Q1
D P3
C L
CLOCK
13
DSR
Q2
DSL
C L
S0
12
S1 Q3
R
C L
8 V SS
500 µF
I D
Serial Load
PULSE
GENERATOR
NOTE: Interchange DSR with DSL and S0 with
S1 for testing shift left.
t h
1/f cl
t PHL
t THL
t PHL
50%
t WL
20 ns 20 ns
90%
CLOCK
10%
50%
1/f
DSR
Q n
MOTOROLA CMOS LOGIC DATA
V DD
16
3 15
D P0 Q0
4
C L
D P1
5
D P2
14
Q1
6
D P3
C L
11
CLOCK
2
13
DSR
Q2
7
DSL
C L
9
S0
10 12
S1 Q3
R
C L
1
8 V SS
V DD
V SS
V DD
V SS
V OH
V OL
t rem
V DD
V SS
V DD
V SS
V DD
V SS
V OH
V OL