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PULSE
GENERATOR
LOGIC DIAGRAM
2
B
14
A
6
X0
5
X1
4
X2
3
X3
10
Y0
11
Y1
12
Y2
13
Y3
MC14539B
6–376
V DD
0.01 µF
500 µF
I D
CERAMIC
A
B
Z
ST
X0
X1
X2
X3
ST
Y0
Y1
W
Y2
Y3
V SS
Figure 2. Power Dissipation Test Circuit and Waveform
ST
1
15
ST
20 ns
90%
50%
10%
V in
C L
50% DUTY CYCLE
C L
7
Z
9
W
MOTOROLA CMOS LOGIC DATA
20 ns
V DD
V SS
PIN ASSIGNMENT
ST
1
16
V DD
B
2
15
ST
X3
3
14
A
X2
4
13
Y3
X1
5
12
Y2
X0
6
11
Y1
Z
7
10
Y0
V SS
8
9
W
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