Motorola CMOS Logic Manual page 325

Q0
Q0
PE
C in
CLOCK
U/D
R
P0
P0
THUMBWHEEL SWITCHES
CLOCK (f in )
RESET
+V DD
OPEN = COUNT
NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example,
the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs P0 to P7. For this divide operation,
both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.
MOTOROLA CMOS LOGIC DATA
Q1 Q2 Q3
Q1 Q2 Q3
C out
L.S.D.
MC14516B
P1 P2 P3
P1 P2 P3
+V DD
(OPEN FOR "0")
Figure 4. Programmable Cascaded Frequency Divider
Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3
PE
C out
C in
M.S.D.
CLOCK
MC14516B
U/D
R
P0 P1 P2 P3
P4 P5 P6 P7
+V DD
W
RESISTORS = 10 k
f in
f out =
n
f out
BUFFER
MC14516B
6–287