Motorola CMOS Logic Manual page 394

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SWITCHING CHARACTERISTICS*
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Characteristic
Output Rise and Fall Time (Pin 13)
t TLH , t THL = (1.5 ns/pF) C L + 25 ns
t TLH , t THL = (0.75 ns/pF) C L + 12.5 ns
t TLH , t THL = (0.55 ns/pF) C L + 9.5 ns
Propagation Delay Time
Clock to Q1, 8–Bypass (Pin 6) High
t PLH , t PHL = (1.7 ns/pF) C L + 1715 ns
t PLH , t PHL = (0.66 ns/pF) C L + 617 ns
t PLH , t PHL = (0.5 ns/pF) C L + 425 ns
Clock to Q1, 8–Bypass (Pin 6) Low
t PLH , t PHL = (1.7 ns/pF) C L + 3715 ns
t PLH , t PHL = (0.66 ns/pF) C L + 1467 ns
t PLH , t PHL = (0.5 ns/pF) C L + 1075 ns
Clock to Q16
t PHL , t PLH = (1.7 ns/pF) C L + 6915 ns
t PHL , t PLH = (0.66 ns/pF) C L + 2967 ns
t PHL , t PLH = (0.5 ns/pF) C L + 2175 ns
Reset to Q n
t PHL = (1.7 ns/pF) C L + 1415 ns
t PHL = (0.66 ns/pF) C L + 567 ns
t PHL = (0.5 ns/pF) C L + 425 ns
Clock Pulse Width
Clock Pulse Frequency
(50% Duty Cycle)
Clock Rise and Fall Time
Reset Pulse Width
* The formulas given are for the typical characteristics only at 25 _ C.
#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V in and
V out should be constrained to the range V SS
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V SS or V DD ). Unused outputs must be left open.
MC14536B
6–356
(C L = 50 pF, T A = 25 _ C)
Symbol
t TLH ,
t THL
t PLH ,
t PHL
t PLH ,
t PHL
t PLH ,
t PHL
t PHL
t WH
f cl
t TLH ,
t THL
t WH
(V in or V out ) V DD .
V DD Min Typ #
5.0 — 100
10 — 50
15 — 40
5.0 — 1800
10 — 650
15 — 450
5.0 — 3.8
10 — 1.5
15 — 1.1
5.0 — 7.0
10 — 3.0
15 — 2.2
5.0 — 1500
10 — 600
15 — 450
5.0 600 300
10 200 100
15 170 85
5.0 — 1.2
10 — 3.0
15 — 5.0
5.0
10 No Limit
15
5.0 1000 500
10 400 200
15 300 150
PIN ASSIGNMENT
SET
RESET
IN 1
OUT 1
OUT 2
8–BYPASS
CLOCK INH
V SS
MOTOROLA CMOS LOGIC DATA
Max Unit
ns
200
100
80
ns
3600
1300
1000
µs
7.6
3.0
2.3
µs
14
6.0
4.5
ns
3000
1200
900
— ns
—
—
0.4 MHz
1.5
2.0
—
— ns
—
—
1 16 V DD
2 15 MONO IN
3 14 OSC INH
4 13 DECODE
5 12 D
6 11 C
7 10 B
8 9 A