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Motorola CMOS Logic Manual page 366

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Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
ELECTRICAL CHARACTERISTICS
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
Characteristic
SUPPLY REQUIREMENTS (Voltages Referenced to V EE )
Power Supply Voltage
Range
Quiescent Current Per
Package
Total Supply Current
(Dynamic Plus
Quiescent, Per Package
CONTROL INPUTS — INHIBIT, A, B (Voltages Referenced to V SS )
Low–Level Input Voltage
High–Level Input Voltage
Input Leakage Current
Input Capacitance
SWITCHES IN/OUT AND COMMONS OUT/IN — W, Z (Voltages Referenced to V EE )
Recommended Peak–to–
Peak Voltage Into or
Out of the Switch
Recommended Static or
Dynamic Voltage
Across the Switch**
(Figure 5)
Output Offset Voltage
ON Resistance
∆ON Resistance Between
Any Two Channels
in the Same Package
Off–Channel Leakage
Current (Figure 10)
Capacitance, Switch I/O
Capacitance, Common O/I
Capacitance, Feedthrough
(Channel Off)
#Data labelled "Typ" is not to be used for design purposes, but is intended as an indication of the IC's potential performance.
** For voltage drops across the switch (∆V switch ) > 600 mV ( > 300 mV at high temperature), excessive V DD current may be drawn; i.e. the
current out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.)
MC14529B
6–328
Symbol
V DD
Test Conditions
V DD
V DD – 3.0
V SS
V EE
I DD
5.0
Control Inputs: V in =
10
V SS or V DD ,
15
Switch I/O: V SS
v
V I/O
V DD , and
v
∆V switch
T A = 25 _ C only (The
I D(AV)
5.0
10
channel component,
15
(V in – V out ) / R on , is
not included.)
V IL
5.0
R on = per spec,
10
I off = per spec
15
V IH
5.0
R on = per spec,
10
I off = per spec
15
I in
15
V in = 0 or V DD
C in
V I/O
Channel On or Off
∆V switch
Channel On
V OO
V in = 0 V, No Load
v
∆V switch
R on
10
500 mV**,
15
V in = V IL or V IH
(Control), and V in =
0 to V DD (Switch)
∆R on
10
15
I off
15
V in = V IL or V IH
(Control) Channel to
Channel or Any One
Channel
C I/O
Inhibit = V DD
C O/I
Inhibit = V DD
C I/O
Pins Not Adjacent
Pins Adjacent
– 55 _ C
Min
Max
Min
3.0
18
3.0
1.0
1.0
v
2.0
500 mV**
Typical
1.5
3.0
4.0
3.5
3.5
7.0
7.0
11
11
0.1
0
V DD
0
0
600
0
400
240
100
25 _ C
125 _ C
Typ #
Max
Min
Max
18
3.0
18
0.005
1.0
60
0.010
1.0
60
0.015
2.0
120
(0.07 µA/kHz) f + I DD
(0.20 µA/kHz) f + I DD
(0.36 µA/kHz) f + I DD
2.25
1.5
1.5
4.50
3.0
3.0
6.75
4.0
4.0
2.75
3.5
5.50
7.0
8.25
11
0.00001
0.1
1.0
5.0
7.5
V DD
0
V DD
600
0
300
10
120
480
560
80
270
350
15
10
0.05
100
1000
8.0
20
0.15
0.47
MOTOROLA CMOS LOGIC DATA
Unit
V
µA
µA
V
V
µA
pF
V p–p
mV
µV
nA
pF
pF
pF

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