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TYPICAL B–SERIES GATE CHARACTERISTICS (cont'd)
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
5.0
4.0
3.0
2.0
1.0
0
0
1.0
2.0
3.0
V in , INPUT VOLTAGE (Vdc)
Figure 8. V DD = 5.0 Vdc
16
14
12
10
8.0
6.0
4.0
2.0
0
0
2.0
4.0
6.0
V in , INPUT VOLTAGE (Vdc)
Figure 10. V DD = 15 Vdc
V out
V DD
V O
V O
0
(a) Inverting Function
MOTOROLA CMOS LOGIC DATA
VOLTAGE TRANSFER CHARACTERISTICS
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
4.0
5.0
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
8.0
10
V DD
V in
V IL
V IH
V SS = 0 VOLTS DC
Figure 11. DC Noise Immunity
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
10
8.0
6.0
4.0
2.0
0
0
2.0
4.0
6.0
V in , INPUT VOLTAGE (Vdc)
Figure 9. V DD = 10 Vdc
DC NOISE MARGIN
The DC noise margin is defined as the input voltage range
from an ideal "1" or "0" input level which does not produce
output state change(s). The typical and guaranteed limit val-
ues of the input values V IL and V IH for the output(s) to be at a
fixed voltage V O are given in the Electrical Characteristics
table. V IL and V IH are presented graphically in Figure 11.
Guaranteed minimum noise margins for both the "1" and
"0" levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
V out
V DD
V O
V O
0
V IL
V IH
(b) Non–Inverting Function
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
8.0
10
V DD
V in
MC14001B
6–13
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