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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
CMOS MSI
Quad R–S Latches
The MC14043B and MC14044B quad R–S latches are constructed with
MOS P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each latch has an independent Q output and set and
reset inputs. The Q outputs are gated through three–state buffers having a
common enable input. The outputs are enabled with a logical "1" or high on
the enable input; a logical "0" or low disconnects the latch from the Q
outputs, resulting in an open circuit at the Q outputs.
Double Diode Input Protection
Three–State Outputs with Common Enable
Outputs Capable of Driving Two Low–power TTL Loads or One Low–
Power Schottky TTL Load Over the Rated Temperature Range
Supply Voltage Range = 3.0 Vdc to 18 Vdc
MC14043B
4
S0
3
R0
6
S1
7
R1
12
S2
11
R2
14
S3
15
R3
5
ENABLE
MC14043B MC14044B
6–116
2
Q0
9
Q1
V DD = PIN 16
V SS = PIN 8
NC = PIN 13
10
Q2
TRUTH TABLE
1
Q3
S R E
Q
X X 0
High
Impedance
0
0
1
No Change
0
1
1
0
1
0
1
1
1
1
1
1
X = Don't Care
MC14043B
MC14044B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
T A = – 55 to 125 C for all packages.
MC14044B
4
R0
3
S0
6
R1
7
S1
12
R2
11
S2
14
R3
15
S3
5
ENABLE
MOTOROLA CMOS LOGIC DATA
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
Plastic
Ceramic
SOIC
13
Q0
9
Q1
V DD = PIN 16
V SS = PIN 8
NC = PIN 2
10
Q2
TRUTH TABLE
1
Q3
S R E
Q
X X 0
High
Impedance
0
0
1
0
0
1
1
1
1
0
1
0
1
1
1
No Change
X = Don't Care
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