Motorola CMOS Logic Manual page 323

Q0
PRESET
ENABLE
0 = COUNT
Q0
PE
1 = PRESET
C in
CLOCK
1 = UP
U/D
0 = DOWN
R
P0
P0
CLOCK
RESET
+V DD
OPEN = COUNT
NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) is disabled while C in is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (count
up mode), C out goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.
(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.
MOTOROLA CMOS LOGIC DATA
Q1 Q2 Q3
Q1 Q2 Q3
C out
L.S.D.
MC14516B
P1 P2 P3
P1 P2 P3
+V DD
THUMBWHEEL SWITCHES
(OPEN FOR "0")
Figure 3. Presettable Cascaded 8–Bit Up/Down Counter
Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3
PE
C out
C in
M.S.D.
CLOCK
MC14516B
U/D
R
P0 P1 P2 P3
P4 P5 P6 P7
+V DD
W
RESISTORS = 10 k
TERMINAL COUNT
INDICATOR
MC14516B
6–285