Motorola CMOS Logic Manual page 297

MOTOROLA CMOS LOGIC DATA
Input LE low, and Inputs D, BI and LT high.
f in respect to a system clock.
All outputs connected to respective C L loads.
20 ns
90%
A, B, AND C
50% DUTY CYCLE
ANY OUTPUT
Figure 1. Dynamic Power Dissipation Signal Waveforms
20 ns
INPUT C
t PLH t PHL
50%
OUTPUT g
t TLH
(a) Inputs D and LE low, and Inputs A, B, BI and LT high.
20 ns
LE
10%
t su
50%
INPUT C
OUTPUT g
(b) Input D low, Inputs A, B, BI and LT high.
20 ns
90%
50%
LE
10%
t WL
(c) Data DCBA strobed into latches.
Figure 2. Dynamic Signal Waveforms
20 ns
V DD
50%
10%
1
V SS
2f
V OH
50%
V OL
20 ns
V DD
90%
50%
10%
V SS
V OH
90%
10%
V OL
t THL
V DD
90%
50%
V SS
t h
V DD
V SS
V OH
V OL
20 ns
V DD
V SS
MC14511B
6–259