Motorola CMOS Logic Manual page 211

CLOCK
2
*
SERIAL
DATA IN
15
*
2
OUTPUT
ENABLE
3
4
5
6
7
8
3
*
CLOCK
1
*
STROBE
t WH
3 CLOCK 50%
t su t h
2 DATA IN
1 STROBE
OUTPUT
15
ENABLE
t PLH
³
90%
N Q1 Q7
10%
t TLH t THL
9 Q S
10 Q S
MOTOROLA CMOS LOGIC DATA
BLOCK DIAGRAM
REGISTER STAGE 1
CLOCK
CLOCK CLOCK
CLOCK CLOCK
REGISTER STAGE 2
REGISTER STAGE 3
REGISTER STAGE 4
REGISTER STAGE 5
REGISTER STAGE 6
REGISTER STAGE 7
REGISTER STAGE 8
CLOCK CLOCK
CLOCK
CLOCK
*Input Protection Diodes
STROBE
STROBE
DYNAMIC TIMING DIAGRAM
t WL
t PLH
t PHL
90%
10%
t PLH
50%
50%
LATCH 1
STROBE
STROBE STROBE
STROBE
LATCH 2 3–STATE BUFFER 2
LATCH 3 3–STATE BUFFER 3
LATCH 4 3–STATE BUFFER 4
LATCH 5 3–STATE BUFFER 5
LATCH 6 3–STATE BUFFER 6
LATCH 7 3–STATE BUFFER 7
LATCH 8
CLOCK
STROBE STROBE
CLOCK
CLOCK
CLOCK
50%
50%
t PZH
t PHZ
90%
10%
t PHL
50%
t PLH
3–STATE BUFFER 1
V DD
4 Q1
5 Q2
6 Q3
7 Q4
14 Q5
13 Q6
12 Q7
11 Q8
3–STATE BUFFER 8
10 Q S
9 Q S
t f
t r
90%
10%
50%
t PLZ t PZL
90%
10%
t PHL
50%
MC14094B
6–173