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8.0
4.0
0
– 4.0
– 8.0
– 12
R TC = 56 kΩ,
R S = 0, f = 10.15 kHz @ V DD = 10 V, T A = 25 C
C = 1000 pF
R S = 120 kΩ, f = 7.8 kHz @ V DD = 10 V, T A = 25 C
– 16
– 55
– 25
0
25
T A , AMBIENT TEMPERATURE ( C)
Figure 4. RC Oscillator Stability
With Auto Reset pin set to a "0" the counter circuit is initial-
ized by turning on power. Or with power already on, the
counter circuit is reset when the Master Reset pin is set to a
"1". Both types of reset will result in synchronously resetting
all counter stages independent of counter state. Auto Reset
pin when set to a "1" provides a low power operation.
The RC oscillator as shown in Figure 3 will oscillate with a
frequency determined by the external RC network i.e.,
1
f =
if (1 kHz
2.3 R tc C tc
and R S
2 R tc
where R S
The time select inputs (A and B) provide a two–bit address
to output any one of four counter stages (2 8 , 2 10 , 2 13 and
2 16 ). The 2 n counts as shown in the Frequency Selection
Table represents the Q output of the N th stage of the counter.
When A is "1", 2 16 is selected for both states of B. However,
R tc
1
C tc
2
3
R S
NC
4
AR
5
MR
6
INPUT
7
t MR
MOTOROLA CMOS LOGIC DATA
TYPICAL RC OSCILLATOR CHARACTERISTICS
V DD = 15 V
10 V
5.0 V
50
75
100
125
OPERATING CHARACTERISTICS
v
v
f
100 kHz)
10 kΩ
DIGITAL TIMER APPLICATION
V DD
14
13
B
12
A
N.C.
11
MODE
10
Q/Q
9
V DD
8
OUTPUT
t + t MR
100
50
20
10
5.0
f AS A FUNCTION
2.0
OF C
(R TC = 56 kΩ)
1.0
(R S = 120 kΩ)
0.5
0.2
0.1
1.0 k
10 k
R TC , RESISTANCE (OHMS)
0.0001
0.001
C, CAPACITANCE (µF)
Figure 5. RC Oscillator Frequency as a
Function of R tc and C tc
when B is "0", normal counting is interrupted and the 9th
counter stage receives its clock directly from the oscillator
(i.e., effectively outputting 2 8 ).
The Q/Q select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q select pin is set to a "0" the Q output is a "0", corre-
spondingly when Q/Q select pin is set to a "1" the Q output is
a "1".
When the mode control pin is set to a "1", the selected
count is continually transmitted to the output. But, with mode
pin "0" and after a reset condition the R S flip–flop (see Ex-
panded Block Diagram) resets, counting commences, and
after 2 n–1 counts the R S flip–flop sets which causes the out-
put to change state. Hence, after another 2 n–1 counts the
output will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to reset
the single cycle operation.
When Master Reset (MR) receives a positive pulse, the in-
ternal counters and latch are reset. The Q output goes high
and remains high until the selected (via A and B) number of
clock pulses are counted, the Q output then goes low and re-
mains low until another input pulse is received.
This "one shot" is fully retriggerable and as accurate as the
input frequency. An external clock can be used (pin 3 is the
clock input, pins 1 and 2 are outputs) if additional accuracy is
needed.
Notice that a setup time equal to the desired pulse width
output is required immediately following initial power up, dur-
ing which time Q output will be high.
V DD = 10 V
f AS A FUNCTION
OF R TC
(C = 1000 pF)
(R S 2R TC )
100 k
1.0 m
0.01
0.1
MC14541B
6–381
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