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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Binary to 1-of-4
Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with complementary
MOS (CMOS) enhancement mode devices. Each Decoder/Demultiplexer
has two select inputs (A and B), an active low Enable input (E), and four
mutually exclusive outputs (Q0, Q1, Q2, Q3). The MC14555B has the
selected output go to the "high" state, and the MC14556B has the selected
output go to the "low" state. Expanded decoding such as binary–to–hexade-
cimal (1–of–16), etc., can be achieved by using other MC14555B or
MC14556B devices.
Applications include code conversion, address decoding, memory selec-
tion control, and demultiplexing (using the Enable input as a data input) in
digital data transmission systems.
Diode Protection on All Inputs
Active High or Active Low Outputs
Expandable
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
MAXIMUM RATINGS*
(Voltages Referenced to V SS )
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
Symbol
Parameter
V DD
DC Supply Voltage
V in , V out
Input or Output Voltage (DC or Transient)
I in , I out
Input or Output Current (DC or Transient),
per Pin
P D
Power Dissipation, per Package†
T stg
Storage Temperature
T L
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
"P and D/DW" Packages: – 7.0 mW/C From 65 _ C To 125 _ C Ceramic
"L" Packages: – 12 mW/ _ C From 100 _ C To 125 _ C
MC14555B
Q0
2
A
Q1
3
B
Q2
1
E
Q3
Q0
14
A
Q1
13
B
Q2
15
E
Q3
MC14555B MC14556B
6–422
Value
– 0.5 to + 18.0
– 0.5 to V DD + 0.5
500
– 65 to + 150
260
BLOCK DIAGRAM
MC14556B
4
2
A
5
3
B
6
1
E
7
12
14
A
11
13
B
10
15
E
9
V DD = PIN 16
V SS = PIN 8
T A = – 55 to 125 C for all packages.
Unit
V
Inputs
V
Enable
E
10
mA
0
0
mW
0
0
_ C
1
_ C
X = Don't Care
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, V in and V out should be constrained
to the range V SS
Q0
4
Unused inputs must always be tied to an
Q1
5
appropriate logic voltage level (e.g., either V SS
Q2
6
or V DD ). Unused outputs must be left open.
Q3
7
12
Q0
11
Q1
Q2
10
9
Q3
MC14555B
MC14556B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
Plastic
MC14XXXBCL
Ceramic
MC14XXXBD
SOIC
TRUTH TABLE
Outputs
Select
MC14555B
MC14556B
B
A
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0
0
0
0
0
1
1
1
0
1
0
0
1
0
1
1
1
0
0
1
0
0
1
0
1
1
1
0
0
0
0
1
X
X
0
0
0
0
1
1
v
v
(V in or V out )
V DD .
MOTOROLA CMOS LOGIC DATA
1
0
0
1
1
1
1
1
1
1
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