Motorola CMOS Logic Manual page 157

Set, Reset, Enable, and Switch Conditions for 3–State Tests
Test Enable S1
t PZH Open
t PZL Closed
t PHZ Open
t PLZ Closed
MC14043B
Q3 1
Q0 2
R0 3
S0 4
E 5
S1 6
R1 7
V SS 8
MOTOROLA CMOS LOGIC DATA
THREE–STATE ENABLE/DISABLE DELAYS
MC14043B
S2 Q S R
Closed A V DD V SS
Open B V SS V DD
Closed A V DD V SS
Open B V SS V DD
ENABLE
50%
t PZH
Q A
10%
t PZL
Q B
PIN ASSIGNMENT
16 V DD
15 R3
14 S3
13 NC
12 S2
11 R2
10 Q2
9 Q1
NC = NO CONNECTION
MC14044B
S R
V SS V DD
TO
V DD V SS
OUTPUT
UNDER
V SS V DD
TEST
V DD V SS
V DD
V SS
V DD
90%
V OL
t PHZ
t PLZ V OH
10%
V SS
MC14044B
Q3 1
NC 2
S0 3
R0 4
E 5
R1 6
S1 7
V SS 8
V DD
S1
1 k
C L
50 pF
S2
V SS
16 V DD
15 S3
14 R3
13 Q0
12 R2
11 S2
10 Q2
9 Q1
MC14043B MC14044B
6–119