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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Phase Comparator and
Programmable Counters
The MC14568B consists of a phase comparator, a divide–by–4, 16, 64 or
100 counter and a programmable divide–by–N 4–bit binary counter (all
positive–edge triggered) constructed with MOS P–channel and N–channel
enhancement mode devices (complementary MOS) in a monolithic structure.
The MC14568B has been designed for use in conjunction with a
programmable divide–by–N counter for frequency synthesizers and phase–
locked loop applications requiring low power dissipation and/or high noise
immunity.
This device can be used with both counters cascaded and the output of
the second counter connected to the phase comparator (CTL high), or used
independently of the programmable divide–by–N counter, for example
cascaded with a MC14569B, MC14522B or MC14526B (CTL low).
Supply Voltage Range = 3.0 to 18 V
Capable of Driving Two Low–Power TTL Loads, One Low–Power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range.
Chip Complexity: 549 FETs or 137 Equivalent Gates
MAXIMUM RATINGS*
(Voltages referenced to V SS )
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
Rating
DC Supply Voltage
Input Voltage, All Inputs
DC Input Current, per Pin
Power Dissipation, per Package†
Operating Temperature Range
Storage Temperature Range
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic "P and D/DW" Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
Ceramic "L" Packages: – 12 mW/ _ C From 100 _ C To 125 _ C
BLOCK DIAGRAM
PC in 14
A
(REF.)
B
TG
TG
C1 9
CTL 15
"0" 3
PROGRAMMABLE
PE 2
D P3
V DD = PIN 16
4
V SS = PIN 8
MOTOROLA CMOS LOGIC DATA
Symbol
Value
V DD
– 0.5 to + 18
V in
– 0.5 to V DD + 0.5
I in
P D
T A
– 55 to + 125
T stg
– 65 to + 150
PHASE
COMPARATOR
COUNTER D1
TG
4–BIT
COUNTER D2
D P0
5
6
7
D P2 D P1
Unit
Vdc
Vdc
10
mAdc
500
mW
_ C
_ C
13 PC out
12 LD
CTL HIGH
11 G
PC in
10 F
P/C
C1
D1
1 Q1/C2
D2
"0"
MC14568B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
Plastic
MC14XXXBCL
Ceramic
MC14XXXBD
SOIC
T A = – 55 to 125 C for all packages.
TRUTH TABLE
F
G
Division Ratio
Pin 10
Pin 11
of Counter D1
0
0
4
0
1
16
1
0
64
1
1
100
The divide by zero state on the pro-
grammable divide–by–N 4–bit binary
counter, D2, is illegal.
CTL LOW
PC out
PC in
P/C
LD
C1
D1
"0"
D2
Q1/C2
MC14568B
PC out
LD
Q1/C2
6–461
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