Motorola CMOS Logic Manual page 348

V DD = –V GS
CF Q0
PE
Q1
P0
P1
P2 Q2
P3
RESET Q3
INHIBIT
CLOCK "0"
V SS
Figure 1. Typical Output Source
Characteristics Test Circuit
V DD
Q0
CF
PE
Q1
P0
P1
Q2
P2
P3
Q3
RESET
INHIBIT
"0"
CLOCK
C L
V SS C L
PULSE
GENERATOR
20 ns
CLOCK
50%
VARIABLE
WIDTH
Figure 3. Power Dissipation
MC14522B MC14526B
6–310
V OH
I OH
EXTERNAL
POWER
SUPPLY
C L
C L
C L
20 ns
V DD
90%
10%
V SS
50% DUTY CYCLE
V DD = V GS
CF Q0
PE
Q1
P0
P1
P2 Q2
P3
RESET Q3
INHIBIT
CLOCK "0"
V SS
Figure 2. Typical Output Sink
Characteristics Test Circuit
Q or "0"
DEVICE
UNDER
TEST
* Includes all probe and jig capacitance.
Figure 4. Test Circuit
MOTOROLA CMOS LOGIC DATA
V OL
I OL
EXTERNAL
POWER
SUPPLY
TEST POINT
C L *