Advertisement
V DD
1
V SS
8
V DS = V OH – V DD
0
V GS = 5.0 Vdc
– 10
– 20
V GS = 10 Vdc
– 30
– 40
V GS = 15 Vdc
– 50
– 10
– 8.0
– 6.0
V DS , DRAIN–TO–SOURCE VOLTAGE (Vdc)
Figure 2. Typical Output Source Characteristics
1200
1100
1000
900
825
800
(L) CERAMIC
740
700
600
500
400
300
(D) SOIC
200
100
0
25
50
75
T A , AMBIENT TEMPERATURE ( C)
Figure 4. Ambient Temperature Power Derating
This device contains circuitry to protect the inputs against damage
due to high static voltages or electric fields referenced to the V SS pin,
only. Extra precautions must be taken to avoid applications of any volt-
age higher than the maximum rated voltages to this high-impedance cir-
cuit. For proper operation, the ranges V SS V in 18 V and V SS V out V DD
are recommended.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V SS or V DD ). Unused outputs must be left open.
MC14049UB
6–132
I OH
V OH
MAXIMUM CURRENT LEVEL
– 4.0
– 2.0
0
(P) PDIP
100
125
150
175
8
160
120
80
40
V GS = 5.0 Vdc
0
0
2.0
V DS , DRAIN–TO–SOURCE VOLTAGE (Vdc)
Figure 3. Typical Output Sink Characteristics
PULSE
GENERATOR
20 ns
INPUT
90%
50%
10%
t PHL
260 mW (L)
175 mW (P)
OUTPUT
120 mW (D)
Figure 5. Switching Time Test Circuit
MOTOROLA CMOS LOGIC DATA
V DD
1
I OL
V OL
V SS
V DD = V OL
V GS = 15 Vdc
V GS = 10 Vdc
MAXIMUM CURRENT LEVEL
4.0
6.0
8.0
V DD
1
V out
V in
C L
8
V SS
20 ns
V DD
V SS
t PLH
V OH
90%
50%
10%
V OL
t THL
t TLH
and Waveforms
PIN ASSIGNMENT
V DD
1
16
NC
OUT A
2
15
OUT F
IN A
3
14
IN F
OUT B
4
13
NC
IN B
5
12
OUT E
OUT C
6
11
IN E
IN C
7
10
OUT D
V SS
8
9
IN D
NC = NO CONNECTION
10
Advertisement
