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MOST SIGNIFICANT
DIGIT
1
A
OUT
0
B
0
C
1
1
D
E out
CLOCK
CASC
E in
"9"
ST
CLEAR S
CLOCK
MC14527B
6–320
LEAST SIGNIFICANT
DIGIT
0
A
OUT
0
B
1
C
2
0
D
E out
CLOCK
CASC
E in
"9"
ST
S
CLEAR
CLOCK
OUT
DRM
Figure 4. Two MC14527Bs in Cascade with Preset No. of 94
NOTE: More than two MC14527Bs
may be cascaded using this
configuration.
0
1
2
3
4
5
6
7
8
9
0
2
One of four output pulses contributed by DRM
output for every 100 clock pulses in for preset No. of 94.
MOTOROLA CMOS LOGIC DATA
1
2
3
4
5
6
7
8
9
0
2
to
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