LH75400/01/10/11 (Preliminary) User's Guide
17.3.2.7 Read/Write Load Register 1
LR1 is the Upper 16-bit Read/Write Load Register. Writes to this register load the most-
significant 16 bits of an Intermediate Register. The Intermediate Register is not loaded into
the free-running counter until the rising edge of CLK1HZ. LR0 should be written to first,
followed by LR1, when the counter is to be reinitialized. Reads return the last written value.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
NOTE: The reset value of this register's bits is indeterminate.
BIT
31:16
15:0
31
30
29
28
27
—
—
—
—
—
R
R
R
R
R
15
14
13
12
11
—
—
—
—
—
RW
RW
RW
RW
RW
Table 21. LR1 Register Definitions
NAME
///
Reserved
RTCLR1 RTC Load Register 1 Specifies the upper 16-bit Counter Load Register.
Table 20. LR1 Register
26
25
24
23
///
—
—
—
—
R
R
R
R
10
9
8
7
RTCLR1
—
—
—
—
RW
RW
RW
RW
0xFFFE0000 + 0x18
FUNCTION
6/17/03
Real-Time Clock
22
21
20
19
18
—
—
—
—
—
R
R
R
R
R
6
5
4
3
2
—
—
—
—
—
RW
RW
RW
RW
RW
17
16
—
—
R
R
1
0
—
—
RW
RW
17-9