Port G Data Direction Register; Table 21-31. Pgddr Register; Table 21-32. Pgddr Register Definitions - Sharp Blue Treak LH75400 User Manual

General Purpose Input/Output

21.2.3.15 Port G Data Direction Register

PGDDR is the Port G Data Direction Register. The active bits used in this register are Read/
Write. Bits set in PGDDR set the corresponding PG pin to be an output:
• Bit [7] controls pin 116 when the pin is configured as PG7. It does not control pin 116
when the pin is configured as CTCAP0B or CTCMP0B.
• Bit [6] controls pin 117 when the pin is configured as PG6. It does not control pin 117
when the pin is configured as CTCAP0A or CTCMP0A.
• Bit [5] controls pin 118 when the pin is configured as PG5. It does not control pin 118
when the pin is configured as CTCLK.
• Bit [4] controls pin 120 when the pin is configured as PG4. It does not control pin 120
when the pin is configured for LCDVEEEN or LCDMOD.
• Bit [3] controls pin 121 when the pin is configured as PG3. It does not control pin 121
when the pin is configured as LCDVDDEN.
• Bit [2] controls pin 122 when the pin is configured as PG2. It does not control pin 122
when the pin is configured as LCDDSPLEN or LCDREV.
• Bit [1] controls pin 123 when the pin is configured as PG1. It does not control pin 123
when the pin is configured as LCDCLS.
• Bit [0] controls pin 124 when the pin is configured as PG0. It does not control pin 124
when the pin is configured as LCDPS.
Clearing a bit configures the pin to be an input. A System Reset clears all bits.
NOTE: The LCDMOD, LCDREV, LCDCLS, and LCDPS functions apply to the LH75401 and LH75411
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
21-18
SoC devices only.

Table 21-31. PGDDR Register

31 30 29 28
0 0 0 0
R R R R
15 14 13 12
///
0 0 0 0
R R R R

Table 21-32. PGDDR Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
Port G Output/Input
Port G Data Direction
Bits set = Port G output.
Bits cleared = Port G input.
LH75400/01/10/11 (Preliminary) User's Guide
27 26 25 24 23
///
0 0 0 0 0
R R R R R
11 10 9 8 7
0 0 0 0 0
R R R R RW
0xFFFDC000 + 0x08
6/17/03
22 21 20 19
0 0 0 0
R R R R
6 5 4 3
Port G Data Direction
0 0 0 0
RW RW RW RW RW
FUNCTION
18 17 16
0 0 0
R R R
2 1 0
0 0 0
RW RW