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LH75400/01/10/11 (Preliminary) User's Guide
20.2.2 Status Conditions
UART2 adheres to the following status conditions:
• If the UART fails to detect a 1 for all programmed stop-bit periods following a data frame,
the UART sets the framing-error status for that frame.
• A line break is 0 for all bits (start bit, data bits, parity bit, and stop bits). The UART sets
the line-break status for each frame containing a line break.
• An address/control character marker bit indicates that the character is either a control
character when in Normal Mode or an address character when in µLAN Mode.
• Enabling parity-error detection causes the UART to compare the parity bit in each frame
with the parity required for the hardware. The UART sets the parity-error status for each
frame containing a parity error.
• If a received character has non-identical samples for at least one of its bits, the Received
Character Noisy bit is set.
• If a received character has no parity or framing error, the Received Character OK bit is set.
20.2.3 Disabling the Loading of Incoming Characters
UART2 provides the option of disabling the loading of incoming characters into the
receiver FIFO by using the UNLOCK/LOCK FIFO commands. When the receiver FIFO is
locked, received characters do not load into the FIFO and can be lost if another character
is received. The UNLOCK/LOCK FIFO commands are useful when the CPU is not willing
to receive characters or is waiting for specific control/address characters.
µLAN Mode provides three address-recognition options. Each option varies in the amount
of CPU offload and degree of FIFO control.
• Automatic Mode — the receiver unlocks the FIFO whenever an address match occurs.
• Semi-Automatic Mode — the receiver unlocks the FIFO when an address character is
received, whether it matches or not.
• Manual Mode — the receiver does not control the FIFO unlocking.
The receiver can be configured to be in Control Character Recognition Mode instead of
µLAN Mode. There is no FIFO control in this mode, but the receiver can generate an inter-
rupt when it receives standard ASCII or EBCDIC control characters.
The receiver can also generate an interrupt upon a character match, with either of two
user-defined characters.
6/17/03
UART2
20-5
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