Table of Contents
Advertisement
Introduction
The frequency ranges of the PLL and crystal oscillator together make for a crystal
frequency range of operation that is from 14 MHz to 20 MHz. However, since the UART
clocks are driven by the crystal oscillator, an oscillator frequency of 14.7456 MHz is rec-
ommended for this design (but not required). This frequency can be divided down to the
exact frequencies that a UART needs to achieve modem baud rates. This creates a PLL
output frequency of approximately 103.2192 MHz. The system clock frequency can be set
up to be from divide-by-30 to divide-by-2 (3.44 MHz to 51.6096 MHz using a 14.7456 MHz
crystal) in decrements of two (30, 28, 26, 24...) of the PLL frequency. These devices are
designed to have a maximum operating frequency of 51.6096 MHz. If UART0 and UART1
are to be used, the system clock frequency must not be set any lower than 3/5 of the
frequency applied to the crystal input pin (XTALIN) for proper UART operation.
The SoCs can be configured to operate via an external clock source, bypassing the inter-
nal PLL. This is done by holding TEST2 and TEST1 LOW and nURESET HIGH while
nPOR is active. These signals are latched on the rising edge of nPOR. During this mode
TEST2 must remain LOW, this keeps the PLL in Bypass Mode and XTALIN becomes the
direct clock input. In this mode, the system clock frequency can be set up to be from divide-
by-30 to divide-by-2 in decrements of two (30, 28, 26, 24...) of the XTALIN frequency. It
can have a maximum system clock frequency of 51.6096 MHz and a minimum of zero, as
this is a static design. The device remains in PLL Bypass Mode until power is removed or
nPOR transitions from LOW to HIGH again.
1.8 Reset Strategy
Two external signals, nPOR and nRESETIN, generate resets to the SoCs. If nPOR is
asserted, all internal registers are set to their default state. It is intended to be used as a
Power-On Reset only. If nRESETIN is asserted, all internal registers EXCEPT the JTAG
circuitry within the devices is set to its default state. The amount of time that Power-On
Reset should be held LOW (crystal stabilization time plus 200 µs) varies, depending on the
crystal used.
While nPOR is asserted, nRESETIN defines the Test Mode, if any, into which the devices
are placed. Once nPOR is released, nRESETIN behaves during Reset as described pre-
viously. For more details, see Chapter 9, Reset, Clock, and Power Controller.
The SoCs can generate two types of Internal Resets: System Reset and RTC Reset. A
System Reset refers to an nPOR Reset, an nRESETIN Reset, a Software Reset, or a
Watchdog Timer Reset. For more details about a Watchdog Timer Reset, see Chapter 9.
As previously stated, there are two types of Software Resets. Either type causes a System
Reset. Only one type causes an RTC Reset, which is the only way to reset the RTC. For
more information about Software Resets, see Chapter 9.
The System Reset is brought out to an external pin (nRESETOUT). nRESETOUT is
held asserted for eight system clock cycles following the release of the reset causing the
System Reset.
1-8
LH75400/01/10/11 (Preliminary) User's Guide
7/15/03
Advertisement
Table of Contents
