Pins Pb5/Nwait To Pb0/Ncs1 Resistor Muxing Register; Table 11-18. Pb_Res_Mux Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

11.2.2.7 Pins PB5/nWAIT to PB0/nCS1 Resistor Muxing Register

PB_RES_MUX is the Pins PB5/nWAIT to PB0/nCS1 Resistor Muxing Register. This reg-
ister allows the pull-up/pull-down to be configured as needed. The active bits used in this
register are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:12
11:10
Table 11-17. PB_RES_MUX Register
31 30 29 28
0 0 0 0
R R R R
15 14 13 12
///
0 1 0 1
R R R R RW

Table 11-18. PB_RES_MUX Register Definitions

/// Reserved Writing to these bits has no effect.
Pin PB5/nWAIT Resistor Source
00 = Pull-down
PB5
01 = Pull-up (default)
10 = No pull-up or pull-down
11 = Pull-up
Pin PB4/nBLE1 Resistor Source
00 = Pull-down
9:8 PB4
01 = Pull-up (default)
10 = No pull-up or pull-down
11 = Pull-up
Pin PB3/nBLE0 Resistor Source
00 = Pull-down
7:6 PB3
01 = Pull-up (default)
10 = No pull-up or pull-down
11 = Pull-up
Pin PB2/nCS3 Resistor Source
00 = Pull-down
5:4 PB2
01 = Pull-up (default)
10 = No pull-up or pull-down
11 = Pull-up
Pin PB1/nCS2 Resistor Source
00 = Pull-down
3:2 PB1
01 = Pull-up (default)
10 = No pull-up or pull-down
11 = Pull-up
Pin PB0/nCS1 Resistor Source
00 = Pull-down
1:0 PB0
01 = Pull-up (default)
10 = No pull-up or pull-down
11 = Pull-up
27 26 25 24 23
///
0 0 0 0 0
R R R R R
11 10 9 8 7
PB5 PB4
0 1 0 1 0
RW RW RW RW
0xFFFE5000 + 0x18
DESCRIPTION
6/17/03
I/O Configuration
22 21 20 19
0 0 0 0
R R R R
6 5 4 3
PB3 PB2 PB1
1 0 1 0
RW RW RW RW
18 17 16
0 0 0
R R R
2 1 0
PB0
1 0 1
RW RW RW
11-13