Wdt Theory Of Operation; Wdt Programmer's Model; Wdt Register Summary; Table 16-1. Wdt Register Summary - Sharp Blue Treak LH75400 User Manual

System-on-chip preliminary

Table of Contents

Watchdog Timer

16.2 WDT Theory of Operation

All Control and Status Registers for the Watchdog Timer can be accessed through the

APB. The Watchdog Timer consists of a 32-bit down-counter that causes a selectable

time-out interval to detect malfunctions. The timer needs to be periodically reset by soft-

ware. Failure to do so results in a time-out that causes an interrupt to be taken or a System

Reset to be issued by the RCPC. There are 16 selectable time intervals for a time-out of

See Chapter 9 for a complete description about reset generation.

The base address for the WDT is:

WDT Base Address: 0xFFFE3000

NAME ADDRESS OFFSET TYPE RESET VALUE

system clock cycles.

LH75400/01/10/11 (Preliminary) User's Guide

Watchdog Control Register

Watchdog Counter Reset

Watchdog Register

WDT Counter Section 0

WDT Counter Section 1

WDT Counter Section 2

WDT Counter Section 3