Dma Controller Register Definitions; Source Base Registers; Destination Base Register; Maximum Count Register - Sharp Blue Treak LH75400 User Manual

Direct Memory Access Controller

12.3.2 DMA Controller Register Definitions

12.3.2.1 Source Base Registers

These two 16-bit registers contain the 32-bit source base address for the next DMA trans-
fer. When the DMA Controller is enabled, the content of the Source Base Address Register
is loaded in the Current Source Address Register.

12.3.2.2 Destination Base Register

These two 16-bit registers contain the 32-bit destination base address for the next DMA
transfer. When the DMA Controller is enabled, the content of the Destination Base
Address Register is loaded in the Current Destination Address Register.

12.3.2.3 Maximum Count Register

This register is programmed with the maximum data unit count of the next DMA transfer.
The data unit is equal to the source-to-DMA data width (byte, half-word or word). When the
DMA Controller is enabled, the content of the Maximum Count Register is loaded in the
Terminal Count Register.
If the Maximum count is programmed to '1', it performs a single transfer only and sets the
terminal count. If the maximum count is programmed to '0', the DMA Controller does not
perform any function.
The maximum terminal count is limited by a 16-bit value. (2
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