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Preface
Pin Names
Package pins are named to indicate the signal(s) or functionality available at the pin. If the
signal or function is active LOW, the name is prefixed with a lower-case 'n', such as nCS2.
Multiplexed pins are named to indicate all available functions, such as Pin 30: PB0/nCS1.
These naming conventions help designers recognize and avoid collisions between multi-
plexed functions but can complicate explanatory text, so this Guide uses the name appro-
priate to the context. A discussion of chip selects, for example, would refer to signal nCS1,
but information about PortB, bit 0 would use PB0. Readers must be aware that these are
separate signals, with distinctly different functionality, which happen to be available on the
same pin. Such signals are not simultaneously available at the pin.
Peripheral Devices
These SOCs are built using the ARM7TDMI-S RISC core as a base. Objects within the
chip but external to the core processor and its support devices are referred to throughout
this Guide as 'Peripheral Devices'.
All four SoCs include two buses:
• An Advanced High-Performance Bus (AHB)
• An Advanced Peripheral Bus (APB).
The devices shown on the APB in the block diagrams are an example of 'peripheral devices'
in this document. Devices that are external to the chip are referred to as 'external devices'.
Register Names
In this User's Guide, the terms 'mask' and 'enable' may be used within register names.
Registers may also be named for one function, and at the same time contain or control
other functions.
Register Addresses
The SoCs are memory-mapped with programmable, internal registers that control its oper-
ation. Each internal register is located at a unique address in the memory map and the reg-
isters are generally grouped in the map by subsystem. In this Guide, the addresses for all
registers are expressed as a base address. The base address indicates where in the map
a group of registers begins.
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LH75400/01/10/11 (Preliminary) User's Guide
7/3/03
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