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LH75400/01/10/11 (Preliminary) User's Guide
10.1.7 Sequencing
The sequence of interrupt processing in the SoCs are:
1.
An interrupt is asserted.
2.
One of the appropriate actions occurs:
– If the interrupt is an external interrupt, the interrupt is conditioned by the RCPC to
– If the interrupt is an internal interrupt, the signal into the VIC is an active HIGH.
– If the interrupt is a software interrupt, a bit has been set in the SoftInt Register that
3.
The unmasked results appear in the RawIntr Register (described in Section 10.2.2.3),
and are submitted to an interrupt-enable masking operation. If the signal has been
unmasked (that is, enabled as an interrupt which is indicated by a corresponding bit
having been initialized in the IntEnable Register), the VIC continues processing
the interrupt.
4.
If the signal has been enabled as an interrupt, it is routed according to whether it has
been identified as an FIQ or IRQ in the IntSelect Register (described in
Section 10.2.2.4).
– If it has not been enabled, processing stops. Note that the interrupt is not cleared
– If the interrupt is subsequently enabled, the uncleared interrupt is asserted imme-
5.
If the interrupt has been identified as an FIQ, the active HIGH signal is asserted on
the CPU FIQ input line without further processing.
6.
If the interrupt has been identified as an IRQ, the active HIGH signal is routed for fur-
ther processing by interrupt vector and priority logic.
7.
The interrupt vector logic establishes whether the interrupt has been associated with
a vectored interrupt. If the signal is identified as a source calling for handling by a vec-
tored interrupt 0-15, the signal is routed to the correct vector logic for processing.
8.
If the signal is not identified as a source calling for handling by a particular vectored
interrupt, the signal is treated as a default-vectored interrupt and is routed to the
default-vectored interrupt logic for processing.
9.
For the case where the signal is a vectored interrupt, the value in the associated
VectAddrX Register (described under Section 10.2.2.11) loads into the VectAddr
Register (described under Section 10.2.2.9). The VectAddrX Register is has been ini-
tialized with the entry address of the vectored interrupt handler. The signal itself is
routed to interrupt priority logic within the VIC. The active HIGH output signal from the
priority processing is asserted on the CPU IRQ line.
10. If the signal is a default-vectored interrupt, the processing is similar to that for a vec-
tored interrupt; however, the same vector is used for multiple interrupt source lines.
The value in the DefVectAddr Register (described under Section 10.2.2.10) loads into
the VectAddr Register. The DefVectAddr Register has been initialized with the entry
address of the default-vectored interrupt handler. The signal itself is routed to interrupt
priority logic within the VIC. The active HIGH output signal from the priority processing
is asserted on the CPU IRQ line.
an active HIGH signal into the VIC.
causes the equivalent of an HIGH level interrupt on the associated line.
if it has not been enabled.
diately, producing a spurious interrupt if global interrupts are enabled.
6/17/03
Vectored Interrupt Controller
10-5
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