Table of Contents
Advertisement
LH75400/01/10/11 (Preliminary) User's Guide
18.5.2.2 Control Register 1
CTRL1 is the Control Register 1. CTRL1 contains five bit fields that control various SSP
functions. The active bits used in this register are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:5
4
3
2
1
0
Table 18-5. CTRL1 Register
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
0
0
0
0
0
R
R
R
R
R
Table 18-6. CTRL1 Register Definitions
NAME
///
Reserved Writing to these bits has no effect. Reading returns 0.
Synchronous Serial Port Enable
SSE
0 = SSP operation is disabled.
1 = SSP operation is enabled.
Loopback Mode
0 = Normal serial port operation enabled.
LBM
1 = Output of transmit serial shifter is connected to input of receive serial
shifter internally.
Receive FIFO Overrun Interrupt Enable
0 = Overrun detection is disabled. Overrun condition does not generate
the SSPRORINTR interrupt. Clearing this bit to zero also clears the
RORIE
SSPROINTER if it is already asserted.
1 = Overrun detection is enabled. Overrun condition generates the
SSPRORINTR interrupt.
Transmit FIFO Interrupt Enable
0 = Transmit FIFO half-full or less condition does not generate the
TIE
SSPTXINTR interrupt.
1 = Transmit FIFO half-full or less condition generates the SSPTXINTR interrupt.
Receive FIFO Interrupt Enable
0 = Receive FIFO half-full-or-more condition does not generate the
RIE
SSPRXINTR interrupt.
1 = Receive FIFO half-full-or-more condition generates the SSPRXINTR interrupt.
26
25
24
23
22
///
0
0
0
0
0
R
R
R
R
R
10
9
8
7
6
///
0
0
0
0
0
R
R
R
R
R
0xFFFC6000 + 0x004
DESCRIPTION
6/17/03
Synchronous Serial Port
21
20
19
18
17
0
0
0
0
0
R
R
R
R
R
5
4
3
2
1
SSE
LBM
TIE
0
0
0
0
0
R
RW
RW
RW
RW
16
0
R
0
RIE
0
RW
18-13
Advertisement
Table of Contents
