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UART0 and UART1
19.3.1.3 Flag Register
FR is the Flag Register. After System Reset, TXFF, RXFF, and BUSY are '0', and TXFE
and RXFE are '1'.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:8
7
6
5
4
3
2:0
19-10
31
30
29
28
27
///
///
0
0
0
0
1
R
R
R
R
R
15
14
13
12
11
///
0
0
0
0
0
R
R
R
R
R
Table 19-9. FR Register Definitions
NAME
///
Reserved Do not modify. Read as zero.
Transmit FIFO Empty The meaning of this bit depends on the state of the FEN
bit in the LCR_H Register (see Section 19-16).
TRANSMIT
FIFO EMPTY
FIFO disabled = This bit is set when the Transmit Holding Register is empty.
FIFO enabled = The TXFE bit is set when the transmit FIFO is empty.
Receive FIFO Full The meaning of this bit depends on the state of the FEN bit
in the LCR_H Register (see Section 19-16).
RECEIVE FIFO
FULL
FIFO disabled = This bit is set when the Receive Holding Register is full.
FIFO enabled = RXFF bit is set when the receive FIFO is full.
Transmit FIFO Full The meaning of this bit depends on the state of the FEN
bit in the LCR_H Register (see Section 19.3.1.9).
TRANSMIT
FIFO FULL
FIFO disabled = This bit is set when the Transmit Holding Register is full.
FIFO enabled = The TXFF bit is set when the transmit FIFO is full.
Receive FIFO Empty The meaning of this bit depends on the state of the FEN
bit in the LCR_H Register (see Section 19.3.1.9).
RECEIVE FIFO
EMPTY
FIFO disabled = This bit is set when the Receive Holding Register is empty.
FIFO enabled = The RXFE bit is set when the receive FIFO is empty
UART Busy
1 = UART is busy transmitting data. This bit remains set until the complete byte,
UART BUSY
including all stop bits, has been sent from the Shift Register. This bit is set as
soon as the transmit FIFO becomes non-empty (regardless of whether the
UART is enabled).
///
Reserved Unpredictable when read.
LH75400/01/10/11 (Preliminary) User's Guide
Table 19-8. FR Register
26
25
24
23
///
///
0
1
1
0
R
R
R
R
10
9
8
7
0
0
0
1
R
R
R
R
UART0: 0xFFFC0000 + 0x018
UART1: 0xFFFC1000 + 0x018
DESCRIPTION
7/15/03
22
21
20
19
18
///
0
0
0
0
0
R
R
R
R
R
6
5
4
3
2
0
0
1
0
0
R
R
R
R
R
17
16
0
0
R
R
1
0
///
0
0
R
R
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