Peripheral Clock Control Register 0; Table 9-18. Apbperiphclkctrl0 Register; Table 9-19. Apbperiphclkctrl0 Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

9.3.2.8 Peripheral Clock Control Register 0

APBPeriphClkCtrl0 is the Peripheral Clock Control Register 0. The active bits used in this
register are Read/Write.
This register controls the real-time, U2, U1, and U0 peripheral clocks. When writing to this
register, setting a data bit to one stops the clock of the corresponding peripheral.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS FIELD NAME
31:10
9
8:3
2
1
0

Table 9-18. APBPeriphClkCtrl0 Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 9-19. APBPeriphClkCtrl0 Register Definitions

/// Reserved Writing to these bits has no effect. Reading returns 0.
RTC Clock
RTC
0 = Real-time clock is running.
1 = Stops the real-time clock.
/// Reserved Read as 1, do not modify.
U2 Peripheral Clock
U2
0 = U2 peripheral clock is running.
1 = Stops the U2 peripheral clock.
U1 Peripheral Clock
U1
0 = U1 peripheral clock is running.
1 = Stops the U1 peripheral clock.
U0 Peripheral Clock
U0
0 = U0 peripheral clock is running.
1 = Stops the U0 peripheral clock.
Reset, Clock, and Power Controller
26 25 24 23 22
///
0 0 0 0 0
R R R R R
10 9 8 7 6
RTC
0 1 1 1 1
R RW R R R
0xFFFE2000 + 0x24
DESCRIPTION
7/15/03
21 20 19 18
0 0 0 0
R R R R
5 4 3 2
— U2
1 1 1 1
R R R RW
17 16
0 0
R R
1 0
U1 U0
1 1
RW RW
9-13