LH75400/01/10/11 (Preliminary) User's Guide
10.2.2.9 Vector Address Register
VectAddr is the Vector Address Register. This register contains the ISR address of the cur-
rently active interrupt. Reading from this register provides the address of the ISR, and indi-
cates to the priority hardware that the interrupt is being serviced. Writing to this register
indicates to the priority hardware that the interrupt has been serviced.
The ISR reads the VectAddr Register:
• When an IRQ interrupt is generated at the end of the ISR.
• When the VectAddr Register is written to.
• To update the priority hardware.
Reading or writing to the register at other times can cause incorrect operation.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:0 VectorAddr
Table 10-19. VectAddr Register
31
30
29
28
27
0
0
0
0
0
RW
RW
RW
RW
RW
15
14
13
12
11
0
0
0
0
0
RW
RW
RW
RW
RW
Table 10-20. VectAddr Register Definitions
NAME
ISR Address Contains the address of the currently active ISR. Any writes
to this register clear the interrupt.
26
25
24
23
22
VectorAddr
0
0
0
0
0
RW
RW
RW
RW
RW
10
9
8
7
6
VectorAddr
0
0
0
0
0
RW
RW
RW
RW
RW
0x030
0xFFFFF000 +
DESCRIPTION
6/17/03
Vectored Interrupt Controller
21
20
19
18
0
0
0
0
RW
RW
RW
RW
RW
5
4
3
2
0
0
0
0
RW
RW
RW
RW
RW
17
16
0
0
RW
1
0
0
0
RW
10-17