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LH75400/01/10/11 (Preliminary) User's Guide
18.2 SSP Theory Of Operation
The SSP performs serial-to-parallel conversion on data received from a peripheral device.
The transmit and receive paths are buffered with internal FIFO memories. These memo-
ries can store eight 16-bit values independently in both transmit and receive modes. Serial
data is transmitted on SSPTX and received on SSPRX. For the SSP to behave properly,
all registers must be written to.
During transmission, data writes to the transmit FIFO via the APB interface. The transmit
data is queued up for parallel-to-serial conversion onto the transmit interface. The transmit
logic formats the data into one of three basic frame types:
• Motorola SPI
• Texas Instruments DSP-compatible Synchronous Serial Interface
• National Semiconductor Microwire.
Table 18-1 describes these modes.
For all three formats, the serial clock (SSPCLK) is held inactive while the SSP is idle and
transitions at the programmed frequency only during active transmission of data. The
SSPCLK pin can be HIGH during idle in SPI Mode if the SPO bit in the Control Register is set.
For Motorola SPI and National Semiconductor Microwire frame formats, the serial frame
(SSPFRM) pin is active LOW and asserted (pulled down) during the entire frame transmis-
sion. Both formats output data on the falling edge of the clock and latch input data on the
rising edge of the clock.
MODE
SPI
SSI
Microwire
Table 18-1. Feature Comparison
DESCRIPTION
Lets the SSP communicate with
Motorola SPI-compatible devices.
Lets the SSP communicate
with Texas Instruments DSP-
compatible Serial Synchronous
Interface devices.
Lets the SSP communicate with
National Semiconductor
Microwire-compatible devices.
DATA TRANSFERS
Full-duplex, 4-wire
synchronous
Full-duplex, 4-wire
synchronous
Half-duplex
synchronous, using
8-bit control messages
6/17/03
Synchronous Serial Port
MISCELLANEOUS
Clock polarity and phase
are programmable.
18-3
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