Table of Contents
Advertisement
Chapter 18
Synchronous Serial Port
The Synchronous Serial Port (SSP) is a master-only interface for synchronous serial
communication with slave peripheral devices that have Motorola SPI, National Semicon-
ductor Microwire, or Texas Instruments DSP-compatible synchronous serial interfaces.
Figure 18-1 shows a block diagram of the SSP.
18.1 SSP Features
The SSP block provides the following features.
• Synchronous Serial Interface in Master Only Mode. The SSP performs serial communi-
cations as a master device in one of three modes:
– Motorola SPI
– Texas Instruments DSP-compatible synchronous serial interface
– National Semiconductor Microwire
• Two 16-bit-wide, 8-entry-deep FIFOs, one for transmitting data and one for receiving data:
– The transmit FIFO takes data written to it and transmits it on the serial interface.
– The receive FIFO parallellizes the serial data stream and presents it in a FIFO for
access by other devices.
• If the receive FIFO is not empty, the SSP can assert an interrupt after a specified number
of clock ticks elapses following the start of a receive transfer. This feature permits
interrupt-driven data transfers that are greater than the FIFO watermark, but not an even
multiple of it.
• Programmable clock bit rate.
• Programmable data frame size, from 4 to 16 bits long, depending on the size of data pro-
grammed. Each frame transmits starting with the most-significant bit.
• Four interrupts, each of which can be individually enabled or disabled using the SSP
Control Register bits. A combined interrupt is also generated as an OR function of the
individual interrupt requests.
• Loopback Test Mode.
6/17/03
18-1
Advertisement
Table of Contents
