Sharp Blue Treak LH75400 User Manual page 354

System-on-chip preliminary
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LH75400/01/10/11 (Preliminary) User's Guide
20.3.1.4 Register Bank 3
NAME
CLCF
BACF
BBL
BBH
GIR
BBCF
///
///
TMIE
Table 20-4. Register Bank 3
ADDRESS
DLAB TYPE
OFFSET
0x00
0
RW
0x04
0
RW
0x00
1
RW
0x04
1
RW
0x08
RW
0x0C
RW
0x10
0x14
0x18
RW
RESET
VALUE
0x00
Clocks Configure Register
0x04
BRGA Configuration Register
BRGB Divisor LSB Register. The DLAB bit in the LCR
0x05
Register needs to be set to access this register.
BRGB Divisor MSB Register. The DLAB bit in the
0x00
LCR Register needs to be set to access this register.
General Interrupt Register/Bank Register (same
0x01
register as in bank 0)
0x84
BRGB Configuration Register
Reserved
Reserved
0x00
Timer Interrupt Enable Register
6/17/03
DESCRIPTION
UART2
20-9

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