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General Purpose Input/Output
21.2.3.9 Port E Data Register
PEDR is the Port E Data Register. The active bits used in this register are Read/Write.
Values written to PEDR are output on the PE pins if the corresponding PEDDR Data Direc-
tion bits are set HIGH (port output).
The values read from each bit of this register are determined by the value of the corre-
sponding bit in the Port E Data Direction Register (see Section 21.2.3.11). A read from this
register returns either:
• The last bit value written if the bit is configured as an output.
• The current value on the corresponding port input if the bit is configured as an input.
A System Reset clears all bits.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
21-12
31
30
29
28
27
0
0
0
0
R
R
R
R
15
14
13
12
11
///
0
0
0
0
R
R
R
R
Table 21-20. PEDR Register Definitions
NAME
///
Reserved Writing to these bits has no effect. Reading returns 0.
Port E Input/Output Data Specifies Port E input or output data, depend-
ing on how the value of the corresponding bit in the PEDDR Register is set
(see Section 21.2.3.11).
Port E Data
PEDDR set as output = PEDR sets the value on the GPIO Port E pins.
PEDDR set as input = PEDR reads the value on the GPIO Port E pins.
LH75400/01/10/11 (Preliminary) User's Guide
Table 21-19. PEDR Register
26
25
24
23
///
0
0
0
0
0
R
R
R
R
R
10
9
8
7
0
0
0
0
0
R
R
R
R
RW
0xFFFDD000 + 0x00
FUNCTION
6/17/03
22
21
20
19
18
0
0
0
0
0
R
R
R
R
R
6
5
4
3
2
Port E Data
0
0
0
0
0
RW
RW
RW
RW
RW
17
16
0
0
R
R
1
0
0
0
RW
RW
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