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LH75400/01/10/11 (Preliminary) User's Guide
The UART receiver is in the marking state (i.e., the input is 1) from the time a stop bit is sent
until the time the next start bit is received. When the receiver receives an entire frame, the
UART transfers the received data and the frame status to the receiver FIFO. The receive
FIFO is a 12-bit-wide, 16-word-deep FIFO memory buffer, or a 1-byte-deep holding register.
The start bit works with the UART bit clock to synchronize the receiver with the source driv-
ing the receiver. When the source drives the receiver input from the idle state to 0, the
receiver waits 7/16ths of a bit period, then samples the input three times:
• Once at 7/16ths of the bit period
• Once at 8/16ths of the bit period
• Once at 9/16ths of the bit period.
If the input is 0 for at least two of the three samples, the UART recognizes a start bit. After
recognizing the start bit, the receiver repeats the following sequence until all data bits, any
parity bit, and all stop bits are detected:
1.
Wait 14/16ths of a bit period, then sample the input.
2.
Wait 1/16th of a bit period, then sample the input.
3.
Wait 1/16th of a bit period, then sample the input.
4.
Choose the majority value of the three samples as the input value for that bit period.
After recognizing the final stop bit, the UART stores the received data frames and associ-
ated status bits in the receiver FIFO.
19.2.2 Status Conditions
UARTs 0 and 1 adhere to the following status conditions:
• If a UART fails to detect a 1 for all programmed stop-bit periods following a data frame,
the UART sets the framing-error status for that frame.
• Enabling parity-error detection causes the UART to compare the parity bit in each frame
with the parity required for the hardware. The UART sets the parity-error status for each
frame containing a parity error.
• A line break is 0 for all bits (start bit, data bits, parity bit, and stop bits). The UART sets
the line-break status for each frame containing a line break.
• The overrun-status bit indicates some frames might have been lost immediately preced-
ing the frame with the overrun status.
The overrun status is announced by both the overrun-error bit in the RSR Register and an
overrun-status bit in a frame in the receiver FIFO. If the receiver FIFO is full and another
frame is received, the receiver enters the overrun state and the UART sets the overrun-
error bit in the RSR. The overrun-error bit remains set until a 1 writes to the overrun-error
bit in the ECR Register.
While the receiver FIFO remains full, additional data frames at the receiver unit are lost
and are not stored in the receiver FIFO. When the UART can resume storing frames in the
receiver FIFO, the receiver exits the overrun state. The overrun-status bit in the receiver
FIFO is set in the first frame stored after the overrun.
7/15/03
UART0 and UART1
19-3
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