Timer 0 Status Register; Table 15-10. Status Register; Table 15-11. Status Register Definitions - Sharp Blue Treak LH75400 User Manual

Timers

15.2.2.4 Timer 0 Status Register

The Status Register bits are independent of the individual interrupt enables. They are set
to 1 upon all compare, capture, and overflow occurrences. To clear the status bits, write a
1 to the individual bits. This action clears the bit that was set in the register and clears the
corresponding interrupt, with the following exception. If the timer is stopped and the Timer
0 Compare Register (CMP0 or CMP1) value matches the Timer 0 Counter Register (CNT),
the corresponding status bit cannot be cleared until either the Timer 0 Compare Register
or the Timer 0 Counter Register value is changed.
Writing a 0 to any of the status bits does not affect the corresponding interrupt. Similarly,
writing a 1 to a bit that is not set does not affect the Status Register or interrupt.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS FIELD NAME
15-14

Table 15-10. Status Register

31 30 29 28
0 0 0 0
R R R R
15 14 13 12
///
0 0 0 0
R R R R

Table 15-11. Status Register Definitions

31:8 /// Reserved Read as zero.
7 CAP4_ST Timer 0 Capture 4 Status To clear, write 1.
6 CAP3_ST Timer 0 Capture 3 Status To clear, write 1.
5 CAP2_ST Timer 0 Capture 2 Status To clear, write 1.
4 CAP1_ST Timer 0 Capture 1 Status To clear, write 1.
3 CAP0_ST Timer 0 Capture 0 Status To clear, write 1.
2 CMP1_ST Timer 0 Compare 1 Status To clear, write 1.
1 CMP0_ST Timer 0 Compare 0 Status To clear, write 1.
0 OVF_ST Timer 0 Overflow Status To clear, write 1.
LH75400/01/10/11 (Preliminary) User's Guide
27 26 25 24 23
///
0 0 0 0 0
R R R R R
11 10 9 8 7
0 0 0 0 0
R R R R RW
0xFFFC4000 + 0x0C
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
R R
1 0
0 0
RW RW