Pins Pe7/Ssprm To Pd0/Int0 Muxing Register; Table 11-7. Pe_Mux Register (Lh75401 And Lh75400); Table 11-8. Pe_Mux Register (Lh75410 And Lh75411) - Sharp Blue Treak LH75400 User Manual

I/O Configuration

11.2.2.3 Pins PE7/SSPRM to PD0/INT0 Muxing Register

PE_MUX is the Pins PE7/SSPRM to PD0/INT0 Muxing Register. This register allows the
secondary function of the pins to be configured as GPIO. The active bits used in this reg-
ister are Read/Write.
The functions of bits [5:2] vary among all four SoCs:
• LH75401 and LH75400: bits [5:4] are assigned CANTX functions and bits [3:2] are
assigned CANRX functions.
• LH75410 and LH75411: bits [5:2] are reserved; always write 0.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
11-6

Table 11-7. PE_MUX Register (LH75401 and LH75400)

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 11-8. PE_MUX Register (LH75410 and LH75411)

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23 22
///
0 0 0 0
R R R R R
10 9 8 7
0 0 0 0
R RW RW RW RW
0xFFFE5000 + 0x08
26 25 24 23 22
///
0 0 0 0
R R R R R
10 9 8 7
0 0 0 0
R RW RW RW RW
0xFFFE5000 + 0x08
6/17/03
21 20 19 18
0 0 0 0 0
R R R R
6 5 4 3 2
CANTX CANRX
0 0 0 0 0
RW RW RW RW
21 20 19 18
0 0 0 0 0
R R R R
6 5 4 3 2
///
0 0 0 0 0
RW RW RW RW
17 16
0 0
R R
1 0
0 0
RW RW
17 16
0 0
R R
1 0
0 0
RW RW