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LH75400/01/10/11 (Preliminary) User's Guide
1.5.1 Linear Regulator Power
When the linear regulator is enabled, the 1.8 V power pins (VDDC) are outputs of the reg-
ulator. This allows regulator operation to be verified. An external low ESR capacitor must
be tied to the regulator output for stability. If the regulator is disabled, the 1.8 V power pins
are used as inputs and an external 1.8 V supply must be provided.
The linear regulator provides an ENABLE input that is tied to the LINREGEN pin. The linear
regulator is enabled by holding LINREGEN HIGH. The linear regulator is disabled by hold-
ing LINREGEN LOW. The LINREGEN input buffer uses an internal pull-up resistor, making
a connection to LINREGEN unnecessary to have the linear regulator enabled as default.
Proper power-up sequencing for the SoC must be considered when employing the linear
regulator. In order to ensure this takes place, nPOR must be held LOW until the linear reg-
ulator has ramped up to an acceptable operating voltage.
Table 1-4 lists the linear regulator ramp-up time.
1.5.1.1 PLL Power
The PLL requires a 1.8 V supply.
• If the linear regulator is disabled, 1.8 V ±0.18 V must be supplied to pin 85.
• If the linear regulator is enabled, the PLL power supply should come from the VDDC
output(s). In this instance, connect VDDA_PLL to VDDC through the filter.
1.5.1.2 PCB Mounted Analog Power Supply Filter for PLL Usage
Ideally, an Analog Power Supply Filter — a low-pass filter with -3 dB at < 1 kHz and
< -70 dB in the absorption band — should be used. However, real-life components limit the
-3 dB point. A good board layout is vital to achieving good high-frequency absorption. An
R-C or R-L-C filter is usually used, with the 'C' composed of multiple devices to achieve a
wide spectrum of noise absorption. For DC reasons, the series resistance of this filter is
limited; generally, a < 5% voltage drop across this device should be observed under worst-
case conditions. High-quality series inductors should not be used without a series resistor;
otherwise, a high-gain series resonator is created.
To achieve the low-frequency cut off, the design needs an electrolytic capacitor in the filter.
As the filter also needs to sustain its attenuation into high frequencies, (e.g., > 100 MHz),
the design needs at least one non-electrolytic capacitor in parallel. The leads of the high-
frequency capacitor(s) must be kept short.
Board layout around this high-frequency capacitor, and the path to the pads, is critical. It
is vital that the quiet ground and power are treated like analog signals.
Table 1-4. Linear Regulator Ramp-up Time
DESCRIPTION
Linear regulator stabilization time after power-up
PLL stabilization time after power-up
7/15/03
Introduction
TYP. ( s) MAX. ( s)
200
8.57143
10
1-5
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