Final Masked Interrupts Register; Table 14-23. Interrupt Register; Table 14-24. Interrupt Register Definitions - Sharp Blue Treak LH75400 User Manual

Liquid Crystal Display Controller

14.3.2.10 Final Masked Interrupts Register

The Interrupt Register is a Read Only register. It is a bit-by-bit logical AND of the Raw Inter-
rupt Status Register (see Section 14.3.2.9) and INTRENABLE Register (see
Section 14.3.2.7). Interrupt lines correspond to each interrupt. A logical OR of all interrupts
is provided to the System Interrupt Controller.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
14-18

Table 14-23. Interrupt Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
R R R R R

Table 14-24. Interrupt Register Definitions

BIT NAME
31:5 ///
4 MBERRORINTR AHB master error interrupt status bit
3 VCOMPINTR
2 LNBUINTR
1 FUFINTR
0 ///
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23 22
///
0 0 0 0
R R R R R
10 9 8 7
///
0 0 0 0
R R R R R
0xFFFF4000 + 0x24
DESCRIPTION
Reserved
Vertical compare interrupt status bit
LCD next base address update interrupt status bit
FIFO underflow interrupt status bit
Reserved
6/17/03
21 20 19 18
0 0 0 0 0
R R R R
6 5 4 3 2
0 0 0 0 0
R R R R
17 16
0 0
R R
1 0
///
0 0
R R