Lcd Panel Parameters, Lcd Panel Power, And Clcdc Control Register - Sharp Blue Treak LH75400 User Manual

Color Liquid Crystal Display Controller
13.3.2.8 LCD Panel Parameters, LCD Panel Power, and
CLCDC Control Register
Ctrl is a Read/Write register that controls the mode in which the CLCDC operates. The
active bits used in this register are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:17
16
15
14
13:12
11
10:9
13-18
31 30 29 28 27
0 0 0 0
R R R R
15 14 13 12 11
///
0 0 0 0
RW RW RW RW RW
Table 13-23. Ctrl Register Definitions
NAME
///
Reserved Writing to these bits has no effect. Reading returns 0.
LCD DMA FIFO Watermark Level
0 = HBUSREQM is raised when either of the two LCD DMA FIFOs have four or
WATERMARK
more empty locations.
1 = HBUSREQM is raised when either of the LCD DMA FIFOs have eight or more
empty locations.
LCD DMA FIFO Test Mode Enable
0 = LCD DMA FIFO inaccessible to user.
LDmaFIFOTME
1 = LCD DMA FIFO Read/Write access for FIFO RAM testing.
Set this bit only when LCD is disabled via bit [0] of this register.
/// Reserved Writing to this bit has no effect. Reading returns 0.
Generate Interrupt
00 = Generates interrupt at start of vertical synchronization.
LcdVComp
01 = Generates interrupt at start of back porch.
10 = Generates interrupt at start of active video.
11 = Generates interrupt at start of front porch.
LCD Power Enable This bit causes the LCDVDDEN pin to toggle.
0 = LCD is OFF, LCDVDDEN pin is LOW.
LcdPwr
1 = LCD is ON, LCDVDDEN pin is HIGH if bit [0] of this register is HIGH. When
using this setting, set bit [0] to 1.
/// Reserved
LH75400/01/10/11 (Preliminary) User's Guide
Table 13-22. Ctrl Register
26 25 24 23
///
0 0 0 0 0
R R R R R
10 9 8 7
///
0 0 0 0 0
R R RW RW
0xFFFF4000 + 0x1C
DESCRIPTION
7/15/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
/// LcdBpp
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
R RW
1 0
0 0
RW RW