Table of Contents
Advertisement
LH75400/01/10/11 (Preliminary) User's Guide
23.1.4 SAR Architecture
While there are various SAR implementations, the basic architecture is simple. Figure 23-3
shows this architecture.
The analog input voltage (VIN) is held on a track/hold. The N-bit register is set to midscale
(100...0, where the most-significant bit is set to 1) to implement the binary search algo-
rithm. This forces the DAC output (VDAC) to be VREF ÷ 2, where VREF is the reference
voltage provided to the ADC. Then a comparison is performed to determine whether VIN
is less than or greater than VDAC:
• If VIN is less than VDAC, the comparator output is a logic LOW and the most-significant
bit of the N-bit register is cleared to 0.
• If VIN is greater than VDAC, the comparator output is a logic HIGH (or 1) and the most-
significant bit of the N-bit register remains set to 1.
The SAR control logic then moves to the next bit down, forces that bit HIGH, and conducts
another comparison. The SAR control logic repeats this sequence until it reaches the
least-significant bit. When the conversion is complete, the N-bit digital word is available
in the register.
ANALOG IN
TRACK/HOLD
VREF
Figure 23-3. Simplified N-bit SAR Architecture
6/25/03
Analog-to-Digital Converter/Brownout Detector
VIN
COMPARATOR
+
VDAC
_
N-BIT
DAC
N
N-BIT
REGISTER
SAR
LOGIC
DIGITAL DATA OUT
(SERIAL or PARALLEL)
LH754xx-97
23-5
Advertisement
Table of Contents
