Table of Contents
Advertisement
Real-Time Clock
17.2 RTC Theory of Operation
The SoC reads and writes data and control/status information via the AMBA APB interface.
The 32-bit counter increments on successive rising edges of the 1 Hz clock from the
RCPC. This clock is generated in the RCPC by dividing down the 32.768 kHz crystal input
to a 1 Hz frequency. The counter is loaded with a start value by writing to the load registers
LR0 and LR1.
• LR0 loads the least-significant 16 bits.
• LR1 loads the most-significant 16 bits.
When loading a new counter value, write to LR0 first, then to LR1. Note, however, that a
new start value does not load into the counter until the first rising edge of 1 Hz clock after
LR1 is written to. For more information about these registers, refer to Section 17.3.2.6 and
Section 17.3.2.7.
The counter value can be obtained at any time by reading Data Registers DR0 and DR1:
• DR0 contains the lower 16 bits of the counter.
• DR1 contains the upper 16 bits of the counter.
When reading the counter value, read DR0 first. This is because DR1 contains the value
of the upper 16 bits when DR0 was last read, rather than the current value of the upper 16
bits. When the counter reaches the maximum value, 0xFFFFFFFF, it wraps to zero and
continues incrementing. For more information about these registers, refer to
Section 17.3.2.1 and Section 17.3.2.2.
Writing to MR0 and MR1 programs the least-significant 16 bits and most-significant 16 bits,
respectively, of the Match Register. The counter and match values are compared in a com-
parator. When both values are equal, the interrupt RTCINTR is asserted HIGH. The soft-
ware can use the interrupt to implement a basic time alarm function. Writing any data value
to the Interrupt Clear Register, EOI, clears the interrupt. The value in the match register
can be read at any time. For more information about these registers, refer to
Section 17.3.2.3 and Section 17.3.2.4.
When using the RTC, resets that need to be done to the RTC should use bit [3] in the
CTRL Register (see Section 17.3.2.8). Failing to reset the RTC using this bit can cause
unpredictable results.
The RTCINTR interrupt can be masked by writing to the CTRL Register. The status of the
interrupt can be obtained by reading the STAT Register.
17-2
LH75400/01/10/11 (Preliminary) User's Guide
6/17/03
Advertisement
Table of Contents
