Loopback Control Register; Table 20-24. Mctrl Register (Bank 0); Table 20-25. Mctrl Register (Bank 1); Table 20-26. Mctrl Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

20.3.2.8 Loopback Control Register

Register Banks: 0 and 1
MCTRL is the Loopback Control Register. The MCTRL Register places UART 2 into the
Loopback Mode selected with the IMD Register (described in Section 20.3.2.23).
For Bank 0, bit [4] is Read/Write and has a reset value of 0x00. For Bank 1, bit [4] is Read
Only and its reset bits are indeterminate.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR

Table 20-24. MCTRL Register (Bank 0)

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
R R R R R

Table 20-25. MCTRL Register (Bank 1)

31 30 29 28 27
— — — — —
R R R R R
15 14 13 12 11
— — — — —
R R R R R

Table 20-26. MCTRL Register Definitions

BITS NAME
31:5 /// Reserved Do not modify. Read as zero.
Loopback Control Bit Places UART2 into Loopback Mode.
4 LC
0 = Loopback is disabled.
1 = Loopback is enabled.
3:0 /// Reserved Read as zero.
26 25 24 23 22
///
0 0 0 0 0
R R R R R
10 9 8 7 6
///
0 0 0 0 0
R R R R R
0xFFFC2000 + 0x10
26 25 24 23 22
///
— — — — —
R R R R R
10 9 8 7 6
///
— — — — —
R R R R R
0xFFFC2000 + 0x10
DESCRIPTION
6/17/03
UART2
21 20 19 18 17
0 0 0 0 0
R R R R R
5 4 3 2 1
LC ///
0 0 0 0 0
R RW R R R
21 20 19 18 17
— — — — —
R R R R R
5 4 3 2 1
LC ///
— — — — —
R R R R R
16
0
R
0
0
R
16
—
R
0
—
R
20-19