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LH75400/01/10/11 (Preliminary) User's Guide
The RCPC manages five Power Modes:
• Active
• Standby
• Sleep
• Stop1
• Stop2.
These modes let users reduce power consumption as necessary, with each mode provid-
ing greater power savings (see Section 9.2.3 for more information). Active Mode is the nor-
mal operating mode. The other modes are entered from Active Mode via software control.
The RCPC returns to Active Mode upon receiving an interrupt.
NOTE: Be sure there are no transmit or receive operations occurring when the LH75400/01/10/11 SoC
Seven external interrupt sources pass through the RCPC before being sent to the Interrupt
Controller. The interrupts entering the RCPC can be individually programmed to be either
level-sensitive or edge-triggered and either active-HIGH or active-LOW. All interrupts exit-
ing the RCPC are converted to a format compatible with the VIC.
9.2.1 Reset Generation
The RCPC generates System Reset and RTC Reset outputs. The RTC block is reset by
the RTC reset output, with the rest of the chip being reset by the System Reset. The
nRESETOUT output pin is driven by the System Reset. The System Reset and RTC Reset
are asserted by any of the following events:
• An external reset (a logic LOW signal on the external nRESETIN or nPOR input pins)
• A signal from the internal Watchdog Timer
• A Soft Reset.
A Soft Reset differentiates between the System Reset and RTC Reset.
• The System Reset is generated when 0xDEAD or 0xDEAC is written to the
SoftReset Register (see Section 9.3.2.4).
• The RTC Reset is generated only when 0xDEAD is written to the SoftReset Register.
The reset latency depends on the PLL lock state. If the PLL is locked when an external
reset is asserted, the System and RTC Reset outputs hold eight system clock (HCLK)
cycles after the external reset is released. Since the Watchdog Timer and Soft Reset can
be generated only if the system clock is running, the PLL must be locked. If the PLL is not
locked when an external reset is deasserted, the RCPC waits until the PLL acquires lock
and holds eight system clock cycles before releasing the system and RTC Reset outputs.
device enters Standby, Sleep, Stop1, or Stop 2 Mode.
Reset, Clock, and Power Controller
7/15/03
9-3
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