Lower Panel Frame Buffer Base Address Register; Table 14-15. Lpbase Register; Table 14-16. Lpbase Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

14.3.2.6 Lower Panel Frame Buffer Base Address Register

The LPBASE Register is one of two LCD DMA Base Address Registers (the other is
UPBASE). Together with UPBASE, this Read/Write register programs the base address
of the frame buffer.
LPBase is used for the lower panel of dual-panel STN displays. UPBase must be initialized
(and LPBase for dual panels) before enabling the LCDC. Optionally the value can be
changed mid-frame to allow double-buffered video displays to be created. These registers
are copied to the corresponding current registers at each LCD vertical synchronization.
This event causes the LNBU bit and an optional interrupt to be generated. The LNBU bit
indicates that it is safe to update both the UPBASE and LPBASE Registers. The interrupt
can be used to reprogram the base address when generating double-buffered video.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:2 LCDLPBASE
1:0

Table 14-15. LPBASE Register

31 30 29 28 27
0 0 0 0 0
RW RW RW RW RW
15 14 13 12 11
0 0 0 0 0
RW RW RW RW RW

Table 14-16. LPBASE Register Definitions

NAME
LCD Lower Panel Base Address Specifies the starting address of the
lower panel frame data in memory and is word aligned.
/// Reserved Writing to these bits has no effect. Reading returns 0.
Liquid Crystal Display Controller
26 25 24 23 22
LCDLPBASE
0 0 0 0 0
RW RW RW RW RW
10 9 8 7 6
LCDLPBASE
0 0 0 0 0
RW RW RW RW RW
0xFFFF4000 + 0x14
DESCRIPTION
6/17/03
21 20 19 18 17
0 0 0 0 0
RW RW RW RW RW
5 4 3 2 1
0 0 0 0 0
RW RW RW RW R
16
0
RW
0
///
0
R
14-13